Serial Adder

We use sequential circuits to design a 4-bit serial adder of unsigned integers. Unlike combinational circuits, the memory feature of flip flops allows us to define two states

flowchart LR
	Q0((State Q0)) --> |11/0| Q1((State Q1))
	Q1 --> |00/1| Q0
	Q0 --> |00/0,01/1,10/1| Q0
	Q1 --> |01/0,10/0,11/1| Q1

where the XY/Z notation stands for two operands / carry-in. Since the states require only one bit to remember, we only need use one D flip-flop to hold the states. The organization of the adder are drawn as

flowchart LR
    In([In]) --> G[Combinational<br> Circuit G]
    G -->|Qnext| D[D Flip-Flop]
	CLK([CLK]) --> D
    D -->|Q| F[Combinational<br> Circuit F]
    D -->|Q| G
    F --> Out([Out])
	In --> F

The combinational circuit G are defined as

$${\mathrm{Q}}_{\mathrm{next}}=\mathrm{G}(\mathrm{X},\mathrm{Y},\mathrm{Q})=(\mathrm{X}\cdot \mathrm{Y})+(\mathrm{X}\oplus \mathrm{Y})\cdot \mathrm{Q}$$

and the circuit F is

$$\mathrm{Out}=\mathrm{F}(\mathrm{X},\mathrm{Y},\mathrm{Q})=\mathrm{X}\oplus \mathrm{Y}\oplus \mathrm{Q}$$